Silicon Physical Design Engineer

The Facebook Reality Labs Silicon team focuses on delivering Facebooks vision through Augmented Reality (AR). Compute power requirements of Augmented Reality require custom silicon. Facebook Silicon team is driving the state of the art forward with breakthrough work in computer vision, machine learning, mixed reality, graphics, displays, sensors, and new ways to map the human body. Our chips will enable AR devices where our real and virtual world will mix and match throughout the day. We believe the only way to achieve our goals is to look at the entire stack, from transistor, through architecture, firmware, and algorithms. We are looking to hire an experienced silicon physical design technical lead to support our efforts in this regard.

Silicon Physical Design Engineer Responsibilities

• Develop and own physical design implementation of multi-hierarchy low-power designs including physical-aware logic synthesis, design for testability, floorplan, place and route, static timing analysis, IR Drop, EM, and physical verification in advanced technology nodes.

• Resolve design and flow issues related to physical design, identify potential solutions, and drive execution.

• Deliver physical design of an end-to-end IP or integration of ASIC/SoC design.

Minimum Qualifications

• Bachelor's degree in Electrical Engineering or equivalent similar experience.

• 10+ years experience in physical design.

• Understanding of RTL2GDSII flow and design tapeouts in 16nm/14nm or below process technologies.

• Experience with low power implementation, power gating, multiple voltage rails, UPF/CPF knowledge.

• Experience working with EDA tools like DC/Genus, ICC2/Innovus, Primetime, Redhawk/Voltus or Calibre.

Preferred Qualifications

• Experience running physical-aware logic synthesis and achieving optimal synthesis QoR on low power designs.

• Knowledge of static timing analysis and concepts, defining timing constraints and exceptions, corners/voltage definitions.

• Experience in Block-level and Full-chip floor-planning and power grid planning.

• Experience with custom or regular clock tree synthesis implementation at block level or top level, and clock power reduction techniques.

• Experience with Python, TCL, Perl programming.